The flag set and test routines

THE 'SIGNAL ..' SUBROUTINES
These subroutines are used to signal various states of the DISCiPLE system. The
corresponding test routines are located from #09F6 and onwards. Clearing is done by
loading 0 into FLASG3, resetting all flags at once. It seems that the flags aren't
used during hook/command code execution.

09CE SIGN_1HAND RST  #18,F_ADDR_RAM      Signal 'there has at least one file
09CF            SET  0,(HL)              been handled'.
09D1            POP  HL
09D2            RET

09D3 SIGN_SERV  RST  #18,F_ADDR_RAM      Signal 'serving the network'.
09D4            SET  1,(HL)
09D6            POP  HL
09D7            RET

09D8 SIGN_STEAL RST  #18,F_ADDR_RAM      Signal 'stealing from or forcing to a
09D9            SET  2,(HL)              pupil'.
09DB            POP  HL
09DC            RET

09DD SIGN_NET   RST  #18,F_ADDR_RAM      Signal 'networking'.
09DE            SET  3,(HL)
09E0            POP  HL
09E1            RET

09E2 SIGN_LOAD  RST  #18,F_ADDR_RAM      Signal 'LOADing'.
09E3            SET  4,(HL)
09E5            POP  HL
09E6            RET

09E7 SIGN_SAVE  RST  #18,F_ADDR_RAM      Signal 'SAVEing'.
09E8            SET  5,(HL)
09EA            POP  HL
09EB            RET

09EC SIGN_MERGE RST  #18,F_ADDR_RAM      Signal 'MERGEing'.
09ED            SET  6,(HL)
09EF            POP  HL
09F0            RET

09F1 SIGN_VERIF RST  #18,F_ADDR_RAM      Signal 'VERIFYing'.
09F2            SET  7,(HL)
09F4            POP  HL
09F5            RET

THE 'TEST ..' SUBROUTINES
These subroutines are used to test various states of the DISCiPLE system.

09F6 TEST_1HAND RST  #18,F_ADDR_RAM
09F7            BIT  0,(HL)
09F9            POP  HL
09FA            RET


09FB TEST_SERV  RST  #18,F_ADDR_RAM
09FC            BIT  1,(HL)
09FE            POP  HL
09FF            RET

0A00 TEST_STEAL RST  #18,F_ADDR_RAM
0A01            BIT  2,(HL)
0A03            POP  HL
0A04            RET

0A05 TEST_NET   RST  #18,F_ADDR_RAM
0A06            BIT  3,(HL)
0A08            POP  HL
0A09            RET

0A0A TEST_LOAD  RST  #18,F_ADDR_RAM
0A0B            BIT  4,(HL)
0A0D            POP  HL
0A0E            RET

0A0F TEST_SAVE  RST  #18,F_ADDR_RAM
0A10            BIT  5,(HL)
0A12            POP  HL
0A13            RET

0A14 TEST_MERGE RST  #18,F_ADDR_RAM
0A15            BIT  6,(HL)
0A17            POP  HL
0A18            RET

0A19 TEST_VERIF RST  #18,F_ADDR_RAM
0A1A            BIT  7,(HL)
0A1C            POP  HL
0A1D            RET